Nagare Labs Unveils Z2RAM Memory Offering SRAM Speed and DRAM Density

Nagare Labs, a Georgia Tech spinout backed by Playground Global and tech veteran Pat Gelsinger, has unveiled Z2RAM, a capacitorless memory technology designed to stack directly on top of AI accelerators. The innovation aims to solve the severe memory bandwidth bottleneck that constrains modern artificial intelligence hardware by merging the high speed of SRAM with the high capacity density of DRAM.

• Nagare Labs is developing Z2RAM to sit directly on top of AI accelerators without an interposer.
• The memory targets 5x the density of SRAM and 14x the speed of DRAM.
• Lab prototypes successfully retain data at 85 degrees Celsius for over 300 seconds.

Architecture and Technical Design of Z2RAM Nagare describes Z2RAM using a structure of "two transistors and a shield, no capacitor." A write transistor places a charge on a storage node, a shield blocks interference from neighboring cells, and a read transistor senses the state without draining the charge. This gain-cell design eliminates the destructive reads and write-back cycles typical of standard DRAM, aiming for energy consumption well under a picojoule per bit. The startup plans to deposit memory layers directly on top of the accelerator die using standard 300 mm DUV lithography tools without requiring EUV equipment. By patterning multiple layers simultaneously in a single exposure—similar to how 3D NAND flash scales vertically—the company’s roadmap targets stacking over 100 layers with hundreds of thousands of vertical connections to drastically increase capacity within a constrained footprint. ## Thermal Constraints and Technical Hurdles Placing memory directly on top of high-performance compute logic introduces significant thermal challenges. Modern AI accelerators generate intense heat, and DRAM-based stacked solutions generally need to stay at or below 95 degrees Celsius to remain operational. Co-founders Suman Datta and Shimeng Yu have demonstrated three-transistor cell iterations capable of retaining data for over 300 seconds at 85 degrees Celsius, making them viable for last-level cache workloads. Despite promising simulation and laboratory results, the technology remains in the prototype phase. Challenges include reliability issues caused by single-electron effects that can shift threshold voltages and flip stored bits, as well as the lack of industry standards for integrating such memory architectures with accelerators. Furthermore, Nagare currently lacks its own fabrication facility and must secure industrial R&D partners to transition out of the university clean room environment. ## Commercialization Roadmap and Industry Impact Nagare is actively looking for fabrication partners to scale production, pointing to AMD's 3D V-Cache as a successful precedent for memory-on-compute integration. The startup aims to begin sampling Z2RAM tiles within the next four years, with potential commercial production shipments arriving over the coming decade. While previous capacitorless memory concepts like Innovative Silicon's Z-RAM faced commercial hurdles decades ago, the intense compute demands of modern AI have renewed industry interest in such breakthroughs. If Nagare successfully resolves its manufacturing, thermal, and reliability hurdles, Z2RAM could redefine memory hierarchies for future high-performance processors and AI infrastructure.